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Optimized communication architecture of MPSoCs with a hardware scheduler: A system view | IEEE Conference Publication | IEEE Xplore

Optimized communication architecture of MPSoCs with a hardware scheduler: A system view


Abstract:

With increasing complexity of MPSoCs, efficient runtime management of system resources becomes of vital importance for improving the system performance and energy efficie...Show More

Abstract:

With increasing complexity of MPSoCs, efficient runtime management of system resources becomes of vital importance for improving the system performance and energy efficiency. OSIP-an operating system application-specific instruction-set processor - provides a promising solution to this. It delivers high computational performance to deal with dynamic task scheduling and mapping, while still being programmable. However, the distributed computation among the different processing elements introduces complexity to the communication architecture, which tends to become the bottleneck of such systems. In this work, we show a detailed analysis and optimization for the communication architecture of OSIP-based MPSoCs. In particular, the joint effects of OSIP and the communication architecture are investigated from the system point of view.
Date of Conference: 29-30 September 2010
Date Added to IEEE Xplore: 09 November 2010
ISBN Information:
Conference Location: Tampere

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