This paper presents a fourth-order 1-bit continuous time bandpass ΣΔ modulator assigned for radio frequency analog to digital conversion. The constraints imposed on the sampling frequency found with conventional method can be intensely reduced using subsampling process. A single loop architecture with sine shaped feedback DAC is chosen to compensate the subsampling continuous time (CT) bandpass ΣΔ modulator non-idealities such as timing jitter. To demonstrate the efficiency of this approach, simulation results for a single-carrier WCDMA signal at 2.14 GHz with 60 MHz band and a sampling frequency of 778.18 MHz show that the maximum attainable SNDR with the proposed modulator is about 44 dB.