Wavelet-based video compression can provide improved codec and bit rates. The shift-variance problem of the discrete wavelet transform on image sequences, however, may cause large errors in motion estimation in the wavelet domain and thus degrade its performance of video compression. To make the wavelet transform of an image shift-invariant, a large amount of additional computation is required. For this reason a high-speed hardware implementation is necessary. This paper is focused on the VLSI design and implementation of a highly parallel shift-invariant wavelet transform chip. The RTL design, synthesis, simulations, and layout have been completed, and OKI Semiconductor, Inc. is fabricating the chip.