This paper presents a new area-efficient architecture to implement the Euclidean algorithm, which is frequently used in Reed-Solomon decoders. The RS (255,239) decoder using the Euclidean algorithm has been implemented with 0.13 /spl mu/m CMOS technology with a supply voltage of 1.1 V. We investigate hardware complexity, clock frequency and data processing rate for this Euclidean algorithm block. The results show that the total number of gates is about 44,700 and it has a data processing rate of 2.4 Gbits/s at a clock frequency of 300 MHz. As compared to the other RS decoders, it gains significant improvements in hardware complexity and latency.