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Multioperand decimal addition | IEEE Conference Publication | IEEE Xplore

Multioperand decimal addition

Publisher: IEEE

Abstract:

This paper introduces four techniques for performing fast decimal addition on multiple binary coded decimal (BCD) operands. Three of the techniques speculate BCD correcti...View more

Abstract:

This paper introduces four techniques for performing fast decimal addition on multiple binary coded decimal (BCD) operands. Three of the techniques speculate BCD correction values and use chaining to correct intermediate results. The first speculates over one addition. The second speculates over two additions. The third employs multiple instances of the second technique in parallel and then merges the results. The fourth technique uses a binary carry-save adder tree and produces a binary sum. Combinational logic is then used to correct the sum and determine the carry into the next digit. Multioperand adder designs are constructed and synthesized for four to sixteen input operands. Analyses are performed on the synthesis results and the merits of each technique are discussed. Finally, these techniques are compared to previous attempts made at speeding up decimal addition.
Date of Conference: 19-20 February 2004
Date Added to IEEE Xplore: 04 October 2004
Print ISBN:0-7695-2097-9
Publisher: IEEE
Conference Location: Lafayette, LA, USA

References

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