Abstract:
Parallel counters are the building blocks of partial product reduction tree (PPRT) circuits, which are required for high-performance multiplication. In this paper we will...Show MoreMetadata
Abstract:
Parallel counters are the building blocks of partial product reduction tree (PPRT) circuits, which are required for high-performance multiplication. In this paper we will implement novel counters using a hybrid of domino and threshold logic. A test 64 /spl times/ 64 PPRT using these counters was found to reduce latency by 39% and device count by 38% compared to the domino logic equivalent.
Published in: IEEE Computer Society Annual Symposium on VLSI
Date of Conference: 19-20 February 2004
Date Added to IEEE Xplore: 04 October 2004
Print ISBN:0-7695-2097-9
Contents 