Recently, polar code has been identified as one of the channel coding schemes in the 5G wireless communication system. One of the challenges in the hardware design of successive cancellation (SC) polar decoder is to reduce the latency. To achieve this goal, in this paper, we first propose the general sequential logic laws (SLL) of SC decoding. The SLL reflects the timing switch relation between the f and 9 operations at various decoding stages. Guided by the SLL, we design a new low-latency SC decoding architecture. It is a novel reformulation for the last two stages of SC decoding so that four bits can be de decoded simultaneously. A polar SC decoder with code length N = 2¹² is implemented in the Stratix V FPGA to verify the proposed architecture. As a result, 25% decoding latency reduction can be achieved with respect to the already-known mainstream SC decoders.