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SHRCO: Design of an SRAM with High Reliability and Cost Optimization for Safety-Critical Applications | IEEE Conference Publication | IEEE Xplore

SHRCO: Design of an SRAM with High Reliability and Cost Optimization for Safety-Critical Applications

Publisher: IEEE

Abstract:

This paper proposes a novel radiation-hardened high-reliability SRAM cell, namely SHRCO, with 12 transistors for robust value storage as well as 6 transistors for paralle...View more

Abstract:

This paper proposes a novel radiation-hardened high-reliability SRAM cell, namely SHRCO, with 12 transistors for robust value storage as well as 6 transistors for parallel access operations. Using separated and error-interceptive feedback paths, the proposed cell has a complete self-recoverability from single-node upset (SNUs) at all single nodes and an excellent self-recoverability from double-node upsets (DNUs) at a part of node pairs. In addition, the proposed cell has superior access operation speed due to the inclusion of extra parallel access transistors. Simulation results show that the proposed cell has the largest number of node pairs that can self-recover from DNUs. Moreover, compared to the existing radiation-hardened SRAM cells, the proposed cell saves 28% of read time and 3% of write time on average.
Date of Conference: 18-20 August 2024
Date Added to IEEE Xplore: 10 September 2024
ISBN Information:

ISSN Information:

Publisher: IEEE
Conference Location: Changsha, China

References

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