Area efficient high speed elliptic curve cryptoprocessor for random curves | IEEE Conference Publication | IEEE Xplore
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Area efficient high speed elliptic curve cryptoprocessor for random curves


Abstract:

A novel hardware processor to compute elliptic curve scalar multiplication is proposed. It is based on a bit serial systolic architecture which performs both binary field...Show More

Abstract:

A novel hardware processor to compute elliptic curve scalar multiplication is proposed. It is based on a bit serial systolic architecture which performs both binary field division and multiplication by using a single type processing element. The field elements are represented in standard form. This scalable unidirectional bit serial systolic architecture can process finite fields of any dimension and any defining irreducible polynomial. It is optimized to have the least storage space while a clock rate over 700 MHz is achieved in the CMOS 0.18 /spl mu/ technology using standard library cells.
Date of Conference: 05-07 April 2004
Date Added to IEEE Xplore: 24 August 2004
Print ISBN:0-7695-2108-8
Conference Location: Las Vegas, NV, USA

References

References is not available for this document.