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Lowering the error floors of low-density parity-check codes with additional check nodes | IEEE Conference Publication | IEEE Xplore

Lowering the error floors of low-density parity-check codes with additional check nodes


Abstract:

This paper proposes a novel scheme for bit recovery of Low-Density Parity-Check (LDPC) Codes. Firstly, the most erroneous and the most reliable bits are located by search...Show More

Abstract:

This paper proposes a novel scheme for bit recovery of Low-Density Parity-Check (LDPC) Codes. Firstly, the most erroneous and the most reliable bits are located by searching the codeword bits. Subsequently, new check nodes are added to connect them, thus the negative effects of the most erroneous bits along with the corresponding trapping sets are avoided. Eventually, the BER performance is dramatically improved in the error-floor region according to the simulated results. This idea could be a more concise and simple alternative to weaken the effects of trapping sets in LDPC applications.
Date of Conference: 06-10 November 2017
Date Added to IEEE Xplore: 01 February 2018
ISBN Information:
Conference Location: Kaohsiung, Taiwan

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