Abstract:
This paper describes the architecture and hardware implementation of an embedded, low-cost and low-power dense stereo reconstruction system, running at 30 fps at VGA reso...Show MoreMetadata
Abstract:
This paper describes the architecture and hardware implementation of an embedded, low-cost and low-power dense stereo reconstruction system, running at 30 fps at VGA resolution. The processing pipeline includes an initial image rectification stage, a cost generation unit based on the non-parametric census transform, a state-of-the-art Semi-Global cost optimization stage, and a final minimization and noise suppression step. The hardware implementation is based on a Xilinx ZynqTM System-on-Chip, which besides the FPGA provides a physical dual-core ARM CPU, which is exploited for control and to deliver output over the integrated Gigabit Ethernet connection.
Published in: 2014 IEEE Intelligent Vehicles Symposium Proceedings
Date of Conference: 08-11 June 2014
Date Added to IEEE Xplore: 17 July 2014
Electronic ISBN:978-1-4799-3638-0
Print ISSN: 1931-0587