Loading [a11y]/accessibility-menu.js
Hardware acceleration of SVM-based traffic classification on FPGA | IEEE Conference Publication | IEEE Xplore

Hardware acceleration of SVM-based traffic classification on FPGA


Abstract:

Understanding the composition of the Internet traffic has many applications nowadays, mainly tracking bandwidth consuming applications, QoS-based traffic engineering and ...Show More

Abstract:

Understanding the composition of the Internet traffic has many applications nowadays, mainly tracking bandwidth consuming applications, QoS-based traffic engineering and lawful interception of illegal traffic. Although many classification methods such as Support Vector Machines (SVM) have demonstrated their accuracy, not enough attention has been paid to the practical implementation of lightweight classifiers. In this paper, we consider the design of a real-time SVM classifier at many Gbps to allow online detection of categories of applications. Our solution is based on the design of a hardware accelerated SVM classifier on a FPGA board.
Date of Conference: 27-31 August 2012
Date Added to IEEE Xplore: 27 September 2012
ISBN Information:

ISSN Information:

Conference Location: Limassol, Cyprus

References

References is not available for this document.