Abstract:
In this paper, the design and implementation of a Fast Hadamard Transformer (FHT) on a field programmable gate array (FPGA) is described. Two possible schemes which use 2...Show MoreMetadata
Abstract:
In this paper, the design and implementation of a Fast Hadamard Transformer (FHT) on a field programmable gate array (FPGA) is described. Two possible schemes which use 256 and 16 chip input sequences are compared on a Xilinx Virtex-E XCV1000E FPGA. The results indicate that the 16 chip sequence achieves 90% reduction in hardware resources and more than double the maximum frequency of operation as compared to 256 chip sequences. An application of the proposed FHT design used to perform cell search for Wideband Code Division Multiple Access (WCDMA) system is also presented.
Date of Conference: 09-11 June 2003
Date Added to IEEE Xplore: 25 June 2003
Print ISBN:0-7695-1943-1
Print ISSN: 1074-6005