Numerous approximate adders have been proposed in the literature in response to the languishing benefits of technology scaling. However, they have been obtained with an ad-hoc and non-systematic methodology which does not fully exploit the design space possibilities. This paper provides a conceptual framework for the systematic design of approximate adders, including hybrid and non-equally segmented approaches as well as more robust error metrics. The framework discriminates the scenarios, where approximate processing does not provide significant benefits from those where it does; in this later case, it aids to obtain optimal configurations for the adders. Experimental results with a commercial technology assess the significant improvements of our systematic approach. Furthermore, a case study with a processor enhanced with an approximate accelerator highlights the usability of the methods.