Metal-insulator–metal (MIM) capacitors are inevitable and critical passive components in analog, mixed-signal, and memory applications. These capacitors occupy nearly 40% of circuit area among other passive and active components of the integrated circuit (IC). Considering this fact, the International Roadmap for Devices and Systems (IRDS) recognized and recommended the miniaturization of MIM capacitors with high permittivity dielectric materials. For future analog and radio frequency (RF) applications, the IRDS has predicted that MIM capacitors should hold a high capacitance density of $\gt {10}~\text {fF}/\mu \text {m}^{{2}}$ , a low voltage linearity of $\lt {100}~\text {ppm}/\text {V}^{{2}}$ , and a low leakage current density of $\lt {10}~\text {nA}/\text {cm}^{{2}}$ . In this regard, many research works have been carried out over the last few decades with various high-k dielectrics to achieve “low voltage linearity.” However, many of them are facing problems with structural defects, interface traps, and poor polarization process due to limitations of fabrication processes. This article attempts to review the challenges and opportunities involved in the reduction of voltage linearity and leakage of MIM capacitors. Also, this article presents the physical limits and challenges involved in MIM capacitor integration with back end of line (BEOL) process of recent complementary metal-oxide–semiconductor (CMOS) technologies. Using physical modeling, the design formula for low voltage linearity coefficient was derived, which helps IC developers in the design and implementation of highly linear RF-analog and mixed-signal (AMS) systems.