40-Gb/s clock and data recovery (CDR) circuit with an integrated high-precision eye-opening monitor (EOM) circuit and an adaptive control scheme for optimizing the data decision point are presented. An adaptive decision-point control (ADPC) scheme using the EOM feedback overcomes the time-varying waveform distortion due to transmission impairment, which causes severe degradation of bit-error-rate (BER) performance in high-speed (>40 Gb/s) data link systems. A 2.5 times 2.0-mm prototype chip is implemented in 0.18 -mum SiGe BiCMOS technology. The power consumption is 1.6 W with a +3.3-V supply voltage. Stable CDR operation with low-jitter performance (189 fs-rms) and the ADPC scheme using EOM feedback are demonstrated at 40 Gb/s. For a 30% duty-distorted 53 -mV signal, the proposed ADPC scheme drastically reduces the BER to le-12 compared to that (2e-7) without adaptive control. The experimental results demonstrate that the proposed CDR circuit greatly improves BER performance and provides robust CDR operation in high-speed data link systems.