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A 256 mW 40 Mbps Full-HD H.264 High-Profile Codec Featuring a Dual-Macroblock Pipeline Architecture in 65 nm CMOS | IEEE Journals & Magazine | IEEE Xplore

A 256 mW 40 Mbps Full-HD H.264 High-Profile Codec Featuring a Dual-Macroblock Pipeline Architecture in 65 nm CMOS


Abstract:

A video-size-scalable H.264 High-Profile codec including 19 application-specific CPUs for extensibility to multiple standards has been fabricated in 65 nm CMOS. With two...Show More

Abstract:

A video-size-scalable H.264 High-Profile codec including 19 application-specific CPUs for extensibility to multiple standards has been fabricated in 65 nm CMOS. With two parallel pipelines for macroblock processing, the codec consumed 256 mW in real-time encoding of 40 Mbps full-HD (1080p30) video at an operating frequency of 162 MHz.
Published in: IEEE Journal of Solid-State Circuits ( Volume: 44, Issue: 4, April 2009)
Page(s): 1184 - 1191
Date of Publication: 24 March 2009

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