A 12 bit 50 MS/s 1.8 V pipelined CMOS analog-to-digital converter (ADC) based on a fully differential class-AB switched operational amplifier achieves low power consumption with a differential input voltage of 2.4 Vp-p. A global-loop dynamic common-mode feedback circuit enables fully differential class-AB operation with dynamic current switching for power reduction. The prototype ADC shows a peak signal-to-noise-and-distortion ratio of 64.0 dB and a peak spurious-free dynamic range of 76.6 dB for a 31 MHz input signal at 50 MS/s while the measured differential and integral nonlinearities are within ±0.26 LSB and ±0.72 LSB, respectively. The prototype ADC in a 0.18 ¿m 1P6M CMOS process consumes 18.4 mW at 50 MS/s and 1.8 V occupying an active die area of 0.26 mm².