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A 25 MHz Bandwidth 5th-Order Continuous-Time Low-Pass Sigma-Delta Modulator With 67.7 dB SNDR Using Time-Domain Quantization and Feedback | IEEE Journals & Magazine | IEEE Xplore

A 25 MHz Bandwidth 5th-Order Continuous-Time Low-Pass Sigma-Delta Modulator With 67.7 dB SNDR Using Time-Domain Quantization and Feedback


Abstract:

This paper introduces a continuous-time low-pass sigma-delta modulator operating with a seven-phase 400 MHz clocking scheme to control time-based processing in the 3-...Show More

Abstract:

This paper introduces a continuous-time low-pass sigma-delta modulator operating with a seven-phase 400 MHz clocking scheme to control time-based processing in the 3-bit two-step quantizer and main digital-to-analog converter (DAC). An on-chip voltage-controlled oscillator and a complementary injection-locked frequency divider are utilized for low-jitter clock signal generation with multiple phases, allowing 3-bit pulse-width modulated feedback with a single-element DAC to avoid performance degradation from unit element mismatch problems associated with conventional multi-bit DACs.
Published in: IEEE Journal of Solid-State Circuits ( Volume: 45, Issue: 9, September 2010)
Page(s): 1795 - 1808
Date of Publication: 23 August 2010

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