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Design Issues and Considerations for Low-Cost 3-D TSV IC Technology | IEEE Journals & Magazine | IEEE Xplore

Design Issues and Considerations for Low-Cost 3-D TSV IC Technology


Abstract:

In this paper key design issues and considerations of a low-cost 3-D Cu-TSV technology are investigated. The impact of TSV on BEOL interconnect reliability is limited, no...Show More

Abstract:

In this paper key design issues and considerations of a low-cost 3-D Cu-TSV technology are investigated. The impact of TSV on BEOL interconnect reliability is limited, no failures have been observed. The impact of TSV stress on MOS devices causes {\rm Vth} shifts, further analysis is required to understand their importance. Thermal hot spots in 3-D chip stacks cause temperature increases three times higher than in 2-D chips, necessitating a careful thermal floorplanning to avoid thermal failures. We have monitored for ESD during 3-D processing and have found no events take place, however careful further monitoring is required. The noise coupling between two tiers in a 3-D chip-stack is 20 dB lower than in a 2-D SoC, opening opportunities for increased mixed signal system performance. The impact on digital circuit performance of TSVs is accurately modeled with the presented RC model and digital gates can directly drive signals through TSVs at high speed and low power. Experimental results of a 3-D Network-on-Chip implementation demonstrate that the NoC concept can be extended from 2-D SoC to 3-D SoCs at low area (0.018 {\hbox {mm}}^{2} ) and power (3%) overhead.
Published in: IEEE Journal of Solid-State Circuits ( Volume: 46, Issue: 1, January 2011)
Page(s): 293 - 307
Date of Publication: 18 October 2010

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