An ultrawideband transceiver employing chirp pulse modulation is proposed for LDR communication. In contrast to the Gaussian pulse, a transmitted pulse modulated with different chirps can maximize the transmitted energy under low supply voltage and is thus amenable to the voltage scalability of the advanced CMOS technologies. The binary data is encoded with different chirp frequencies and two identical pulses are sent per data bit to enable non-coherent demodulation which simplifies the receiver architecture. A demodulation calibration loop is also incorporated to optimize the SIR performance. In-band/out-of-band SIR as low as -21dB/-59 dB can be tolerated in order to achieve BER better than 10^-3. Implemented in 0.18 μm CMOS, the transceiver can sustain data rates up to 20 Mbps, and achieve energy efficiency of 0.77 nJ/bit for transmitting and 2.7 nJ/bit for receiving under 1.8 V supply.