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Demonstration of Integrated Micro-Electro-Mechanical Relay Circuits for VLSI Applications | IEEE Journals & Magazine | IEEE Xplore

Demonstration of Integrated Micro-Electro-Mechanical Relay Circuits for VLSI Applications


Abstract:

This work presents measured results from test chips containing circuits implemented with micro-electro-mechanical (MEM) relays. The relay circuits designed on these test ...Show More

Abstract:

This work presents measured results from test chips containing circuits implemented with micro-electro-mechanical (MEM) relays. The relay circuits designed on these test chips illustrate a range of important functions necessary for the implementation of integrated VLSI systems and lend insight into circuit design techniques optimized for the physical properties of these devices. To explore these techniques a hybrid electro-mechanical model of the relays' electrical and mechanical characteristics has been developed, correlated to measurements, and then also applied to predict MEM relay performance if the technology were scaled to a 90 nm technology node. A theoretical, scaled, 32-bit MEM relay-based adder, with a single-bit functionality demonstrated by the measured circuits, is found to offer a factor of ten energy efficiency gain over an optimized CMOS adder for sub-20 MOPS throughputs at a moderate increase in area.
Published in: IEEE Journal of Solid-State Circuits ( Volume: 46, Issue: 1, January 2011)
Page(s): 308 - 320
Date of Publication: 01 November 2010

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