A 0.8-mW 5-bit 250-MS/s Time-Interleaved Asynchronous Digital Slope ADC | IEEE Journals & Magazine | IEEE Xplore

A 0.8-mW 5-bit 250-MS/s Time-Interleaved Asynchronous Digital Slope ADC


Abstract:

Slope and digital-ramp converters are normally limited to very low sampling rates, since they require a digital counter at a highly oversampled clock rate. In this work, ...Show More

Abstract:

Slope and digital-ramp converters are normally limited to very low sampling rates, since they require a digital counter at a highly oversampled clock rate. In this work, an asynchronous digital slope architecture is introduced that only requires a nonoversampled clock, thus enabling a much higher speed of operation. At the same time, the low complexity and the inherent accuracy of the slope-architecture enable very good power-efficiency without using complex calibration techniques. A two-channel time-interleaved 5-bit asynchronous digital slope ADC was implemented in a 90-nm CMOS technology and occupies 160 μm × 200 μm. The measured prototype achieves an ENOB of 4.6 bit, while operating at 250 MS/s and consuming 0.8 mW from a 1-V supply.
Published in: IEEE Journal of Solid-State Circuits ( Volume: 46, Issue: 11, November 2011)
Page(s): 2450 - 2457
Date of Publication: 19 September 2011

ISSN Information:


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