Among all the emerging memories, Spin-Transfer Torque Random Access Memory (STT-RAM) has demonstrated many promising features such as fast access speed, nonvolatility, excellent scalability, and compatibility to CMOS process. However, the large process variations of both magnetic tunneling junction (MTJ) and MOS transistors in the scaled technologies severely limit the yield of STT-RAM chips. In this work, we proposed a new sensing scheme, named as nondestructive self-reference sensing, or NSRS, for STT-RAM. By leveraging the different dependencies of the high and low resistance states of MTJs on the cell current amplitude, the proposed NSRS technique can work well at the scenario when bit-to-bit variation of MTJ resistances is large. Furthermore, we proposed three combined magnetic- and circuit-level techniques, including R-I curve skewing, yield-driven cell current selection, and ratio matching, to further improve the sense margin and robustness of NSRS sensing scheme. The measurement results of a 16 Kb STT-RAM test chip show that our proposed nondestructive self-reference sensing technique can reliably readout all the measured memory bits, of which 10% read failure rate was observed by using the conventional sensing technique. The three enhancement technologies ensure a 20 mV minimum sense margin and the whole sensing process can complete within 15 ns.