Abstract:
This paper introduces and demonstrates with high yield a novel concept for the packaging under vacuum of tuning fork quartz XTALs on top of a silicon interposer equipped ...Show MoreMetadata
Abstract:
This paper introduces and demonstrates with high yield a novel concept for the packaging under vacuum of tuning fork quartz XTALs on top of a silicon interposer equipped with TSVs. It paves the way to the implementation of a monolithic timing microsystem where the ASIC is part of the housing of a newly designed tiny 131-kHz XTAL to reach extreme module miniaturization (1.5\,\times\,1.1\,\times\,0.7 mm^{3}) and integrity. As this task is still ongoing, an early demonstration of the generic versatile timing module is presented using a chip-on-board approach with standalone conventionally packaged XTAL and BAW resonators. The module achieves 0.4 \muW power dissipation and {\pm} 2 ppm stability over {-} 40 ^{\circ} C to 85 ^{\circ} C in RTC mode and can deliver on-demand programmable clocks between 1–50 MHz. The latter are obtained either with a RC PLL or after division of the signal obtained from a 2-GHz BAW DCO at a power dissipation of 100 \mu W and 5.3 mW, respectively.
Published in: IEEE Journal of Solid-State Circuits ( Volume: 49, Issue: 1, January 2014)