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A 70 dB DR 10 b 0-to-80 MS/s Current-Integrating SAR ADC With Adaptive Dynamic Range | IEEE Journals & Magazine | IEEE Xplore

A 70 dB DR 10 b 0-to-80 MS/s Current-Integrating SAR ADC With Adaptive Dynamic Range


Abstract:

A charge-domain SAR ADC is presented which integrates the current of a variable-gain transconductor on its sampling capacitor, rather than being driven by a power hungry ...Show More

Abstract:

A charge-domain SAR ADC is presented which integrates the current of a variable-gain transconductor on its sampling capacitor, rather than being driven by a power hungry voltage buffer. The sampling circuit uses nonlinear MOS capacitors as sampling capacitor for passive amplification to relax the comparator noise requirements without compromising linearity. The prototype in 40 nm low power CMOS process consists of a 1.1-17.6 mS transconductor, combined with a 10 b 0-80 MS/s charge-sharing SAR ADC. It achieves 70 dB DR while consuming less than 5.45 mA from a 1.1 V supply and achieves a peak SNDR of 56.85 dB at 40 MS/s.
Published in: IEEE Journal of Solid-State Circuits ( Volume: 49, Issue: 5, May 2014)
Page(s): 1173 - 1183
Date of Publication: 11 March 2014

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