A fractional-N LC-PLL in 28 nm CMOS that uses vertical layout integration techniques to achieve area reduction without performance penalties is proposed. The design utilizes multi-metal layers to vertically integrate dual interposed inductors on top of the active PLL circuit elements, resulting in an area of 0.07 mm². The PLL covers a wide-frequency range from 2.7 GHz to 7 GHz, consuming a total power of 14 mW. At 7 GHz, the RMS jitter is 0.56 ps in integer mode and 1.1 ps in fractional mode.