An 8.2 Gb/s-to-10.3 Gb/s full-rate referenceless CDR in 0.18 μm CMOS is presented. By realizing an asymmetric phase detector transfer curve, the linear CDR's “single-sided” capture range increases, which allows the Hogge phase detector itself to function as a frequency detector, thus eliminating the need for the reference clock and the separate frequency detector in conventional dual-loop CDRs. Robust frequency and phase acquisition is demonstrated. Furthermore, a new phase adjustment mode is added to further improve the jitter tolerance performance. The measurement results show that with a 10.3 Gb/s 2 ³¹-1 PRBS input, the random jitter at the output data is 0.336 ps rms, and the out-of-band jitter tolerance is 0.34 UI p-p.