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A 0.7-V 0.6- <span class="MathJax_Preview">\mu \text{W}</span><script type="math/tex" id="MathJax-Element-1">\mu \text{W}</script> 100-kS/s Low-Power SAR ADC With Statistical Estimation-Based Noise Reduction | IEEE Journals & Magazine | IEEE Xplore

A 0.7-V 0.6- \mu \text{W} 100-kS/s Low-Power SAR ADC With Statistical Estimation-Based Noise Reduction


Abstract:

This paper presents a power-efficient noise reduction technique for successive approximation register analog-to-digital converters (ADCs) based on the statistical estimat...Show More

Abstract:

This paper presents a power-efficient noise reduction technique for successive approximation register analog-to-digital converters (ADCs) based on the statistical estimation theory. It suppresses both comparator noise and quantization error by accurately estimating the ADC conversion residue. It allows a high signal-to-noise ratio (SNR) to be achieved with a noisy low-power comparator and a relatively low resolution digital-to-analog converter (DAC). The proposed technique has low hardware complexity, requiring no change to the standard ADC operation except for repeating the least significant bit (LSB) comparisons. Three estimation schemes are studied and the optimal Bayes estimator is chosen for a prototype 11-b ADC in 65-nm CMOS. The measured SNR is improved by 7 dB with the proposed noise reduction technique. Overall, it achieves 10.5-b effective number of bits while operating at 100 kS/s and consuming 0.6 μW from a 0.7-V power supply.
Published in: IEEE Journal of Solid-State Circuits ( Volume: 52, Issue: 5, May 2017)
Page(s): 1388 - 1398
Date of Publication: 16 February 2017

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