Abstract:
A two-time interleaved pipelined SAR ADC in 16-nm CMOS achieving 11.2-bit ENOB at 300 MS/s is presented. To cancel the signal-dependent voltage ripple on the reference no...Show MoreMetadata
Abstract:
A two-time interleaved pipelined SAR ADC in 16-nm CMOS achieving 11.2-bit ENOB at 300 MS/s is presented. To cancel the signal-dependent voltage ripple on the reference node due to DAC switching, it employs a stabilization scheme based on the use of auxiliary DACs. The charge drawn from the reference becomes signal-independent, greatly reducing the requirements for the reference decoupling capacitance and/or buffers. The technique improves the linearity to levels better than 76-dB harmonic distortion. Power consumption is only 3.6 mW resulting in peak FoMs of 175.5 dB and 5.1 fJ/conv.step.
Published in: IEEE Journal of Solid-State Circuits ( Volume: 53, Issue: 4, April 2018)