A 7.5 Gb/s/pin 8-Gb LPDDR5 SDRAM is implemented in a 1× nm DRAM process. Various techniques are applied to achieve higher bandwidth and lower power than LPDDR4X. To increase data rate, a WCK clocking scheme that is less vulnerable to power noise is adopted and a non-target ODT mode is proposed to reduce reflection noise in a two-rank system. A couple of techniques are proposed for saving power. To reduce self-refresh power, this chip supports deep sleep mode (DSM). In DSM, the leakage current of internal voltages decreases by disabling internal voltage generators that are not related with a self-refresh operation. Dynamic voltage frequency scaling (DVFS) is adopted to reduce read and write operation power and when writing all zeros data, an internal data copy function can be used for reducing write operation power. Last, a ZQ calibration scheme that shares one ZQ resistor (RZQ) and automatically executes ZQ calibration is presented. The proposed LPDDR5 DRAM operates up to 7.5 Gb/s on an automatic test equipment (ATE) and 6.4 Gb/s on a prototype system. Read and write power decrease by 21% and 33% compared to LPDDR4X at 4.266 Gb/s, and self-refresh power is reduced by 25% in DSM.