A 30-GHz Digital Sub-Sampling Fractional-<inline-formula> <tex-math notation="LaTeX">$N$ </tex-math></inline-formula> PLL With −238.6-dB Jitter-Power Figure of Merit in 65-nm LP CMOS

A 30-GHz Digital Sub-Sampling Fractional-- PLL With −238.6-dB Jitter-Power Figure of Merit in 65-nm LP CMOS | IEEE Journals & Magazine | IEEE Xplore