A single-chip CMOS transceiver (TRX) capable of wireless data rates up to 80 Gb/s using part of frequencies (252–279 GHz) covered by IEEE Std 802.15.3d is presented. The TRX chip operates in either transmitter (TX) or receiver (RX) mode at frequencies comparable to ${f_{\mathrm {max}}}$ of the NMOSFET. The TX part adopts mixer-last architecture with four-way power combining using a ring circuit called a double-rat-race. The RX part adopts fundamental-mixer-first direct-conversion architecture. In the RX mode, the TX serves as an LO multiplier chain, which conventionally accounted for a significant part of the RX die area. The double-rat-race, having an improved design than the original one, integrates the TX and RX and also rejects unwanted harmonics generated by the frequency-doubler-based upconversion mixer. Low-loss, low-characteristic-impedance transmission lines are used extensively to combat losses. The TRX was fabricated using a 40-nm CMOS process. The saturated output power of the TX is −1.6 dBm at 265.68 GHz. The mean single-sideband noise figure (SSB NF) of the RX is 22.9 dB. The TX mode and the RX mode consume dc power of 890 and 897 mW, respectively. A wireless data rate of 80 Gb/s between a pair of TRX chips is demonstrated with 16QAM over a distance of 3 cm.