Ultralow-power sensing with inference functionality embedded in sensor nodes is essential for enabling the emerging pervasive intelligence. For acoustic inference sensing, the feature extraction can take advantage of power-efficient analog circuits. However, the existing solutions have been mostly constrained to linear analog signal processing, which largely limits the achievable power efficiency. In this article, we show that tasks like voice activity detection and keyword spotting can well accommodate analog feature extractor’s high nonlinearity, which arises from electronic device physics and circuit design constraints. Applying this principle to a 65-nm CMOS chip implementation, we demonstrate high classification accuracy with nonlinear analog feature extraction consuming only 50 nW. At the end of digital scaling, this study may shed light on the possibility of exploiting the largely relaxed degree of freedom, i.e., linearity, in analog circuit design in the pursuit of extreme power efficiency for designing future inference sensing systems.