This article presents a 71–86 GHz 16-element array receiver application-specified integrated circuit (ASIC) for Massive multiple-input–multiple-output (MIMO) wireless uplink, featuring a multiple-output analog beamformer (BF) supporting up to 16 spatially multiplexed users at the same time. The ASIC includes 16 direct-conversion mixer-first RX front-ends, local oscillator (LO) generation and distribution, and a $16\times 16$ fully connected baseband analog beamformer, which derives each user stream as a linear combination of all the 16 antennas. The 16 mm² 28 nm CMOS ASIC is packaged on an organic interposer including a linear patch antenna array. Over-the-air measurements demonstrate up to 2 Gb/s single-user data-rate, and four simultaneous links at 500 Mb/s each, with number of users and data rate only limited by setup constraints. Circuits are optimized for low power consumption in order to enable scaling to massive arrays, and consumes 1.7 W total power, for a power figure of 7 mW/antenna/user.