This article presents a 15-bit pseudo-pseudo-differential (PPD) incremental zoom analog-to-digital converter (ADC). It employs two single-ended (SE) 3-bit successive-approximation-register (SAR) ADC and a third-order SE incremental $\Delta \Sigma$ ADC to process a pair of differential input signals. A novel three-phase clock helps eliminate the half-cycle delay between the positive and the negative input sampling, boosting this work’s common-mode-rejection ratio (CMRR). Fabricated in 55 nm CMOS technology, the ADC achieves a measured 89.9 dB signal-to-noise ratio (SNR) in a conversion time of 0.378 ms while consuming only $1.07 \mu \text{W}$ from a 1 V supply. This corresponds to a Schreier figure-of-merit (FoM) of 180.8 dB.