We describe the advantages and challenges encountered during the design of wideband continuous-time pipeline (CTP) analog-to-digital converters (ADCs). The converter incorporates an area- and power-efficient foreground technique that exploits thermal noise to estimate the taps of digital reconstruction filters of the pipeline. The design features a half-rate mode that exploits the sharp filtering characteristic of the CTP to reduce the back-end sampling rate, thereby lowering power dissipation. The techniques are applied to a CTP that realizes the equivalent of a cascade of a 106-MHz bandwidth sixth-order Butterworth filter followed by a 12.5-bit 800-MS/s ADC. The CTP, realized in 65-nm CMOS, achieves an ENOB of about 12 bits in a 100-MHz bandwidth and dissipates 59 mW from a 1.2-V supply.