This article presents a discrete-time $\Delta \Sigma$ modulator (DSM) with a wide linear input range and high input impedance for biomedical signal acquisition. The proposed integrated circuit (IC) is based on a 1st-order DSM with 2nd-order noise-shaping (NS)-successive approximation (SAR) for high resolution with high power efficiency, directly converting the small input signal to digital. The first-stage integrator in the DSM is designed to support not only for wide-input swing at low power consumption but also for high input impedance. The input impedance is further boosted by a proposed presampling-based charge-transfer-reduction technique, which does not require any additional amplifiers. It precharges the sampling capacitor with just the previous sampled signal, thus reducing the charge transfer and boosting the input impedance. Besides, we also propose a new truncation-error shaping method. By feeding the truncation error back to the local NS-SAR loop, the truncation error is effectively noise-shaped without using any additional loop, resulting in 4th-order NS. The prototype IC is fabricated in a 65-nm CMOS process. It achieves 94.5-dB signal-to-noise-and-distortion ratio (SNDR) for 1–500-Hz bandwidth with 600-mVPP input applied, resulting in FoMSNDR of 174.3 dB and FoMDR of 175.8 dB. It achieves over 83-dB common-mode rejection ratio (CMRR) and input impedance of 208 $\text{M}\Omega$ at dc and 31.5 $\text{M}\Omega$ at the target bandwidth. Moreover, its artifact tolerance is verified by in vitro and in vivo measurements.