The all-digital fractional-N bang-bang PLL (BBPLL) requires a high-resolution digital-to-time converter (DTC) with complex nonlinearity calibration or compensation. For the design of a DTC-free $\Delta \Sigma$ fractional-N BBPLL, the use of a phase-domain lowpass filter (PDLPF) based on a finite-impulse response (FIR)-embedded injection-locked oscillator (FIR-ILO) is proposed. By integrating the FIR filtering in the ILO-based PDLPF, the quantization noise effect of the $\Delta \Sigma$ modulator is significantly mitigated in the fractional-N BBPLL, resulting in good in-band phase noise and fractional spur performance. A prototype fractional-N BBPLL is implemented in 65-nm CMOS. With the proposed FIR-ILO PDLPF, the in-band phase noise and the fractional spur are improved by more than 25 and 10 dB, respectively. An in-band noise of −96.6 dBc/Hz and a reference spur of −78.7 dBc are achieved at 2.6-GHz output, consuming 4.3 mW from a 0.9-V supply. The proposed FIR-ILO filtering method is useful not only to improve the in-band noise and spur of the fractional-N BBPLL but also to provide an effective way of suppressing the out-of-band noise for conventional fractional-N PLLs.