This work introduces a new hybrid architecture combining a voltage-controlled oscillator (VCO)-based continuous-time (CT) delta-sigma modulator (DSM) with a noise-shaping (NS) successive approximation register (SAR) quantizer. The key innovation is an anti-aliasing filter (AAF) that bridges the VCO front-end with the NS-SAR quantizer, enabling the time-domain information to be directly sampled as the voltage-domain information. The hybrid architecture provides a high-order noise transfer function (NTF) while maintaining simple loop dynamics. The fabricated 28-nm CMOS prototype achieves 84.2-dB signal-to-noise-distortion ratio (SNDR) and 86.8-dB dynamic range (DR) within a 1-MHz bandwidth (BW) while consuming 1.62 mW at 100 MS/s. The corresponding Schreier SNDR figure of merit (FoM) is 172.1 dB. The core circuit occupies only 0.024 mm2. No calibration or coefficient tuning is required.