This article presents a switched-capacitor (SC) delta–sigma modulator (DSM) for low-power and high-precision applications. With a 5-bit noise-shaping (NS) successive-approximation-register (NSSAR) quantizer embedded in the 2nd-order loop filter, the system achieves a stable 3rd-order noise transfer function (NTF) without coefficient scaling. Partial feedback with digital filters is adopted, which only feeds back the 3 MSBs, leading to a fourfold reduction of data-weighted-averaging (DWA) complexity. To mitigate the noise leakage, a gain-boosted two-stage floating inverter amplifier (FIA) with 87.2-dB open-loop gain is proposed with the assistance of the Correlated-level-shifting (CLS) technique. The stability and noise performance of the FIA are also optimized. Fabricated in a 55-nm CMOS process, the prototype analog-to-digital converter (ADC) achieves a measured 93.7-dB signal to noise and distortion ratio (SNDR) in a 10-kHz bandwidth at 800 kS/s at a oversampling ratio (OSR) of 40. With 33.2- $\mu \text{W}$ power consumption, it achieves an SNDR-based Schreier figure of merit (FoM) of 178.5 dB and a Walden FoM of 41.9 fJ/conv, demonstrating state-of-the-art energy efficiency. Furthermore, the prototype exhibits fully dynamic characteristics and capabilities to a higher dynamic range (DR).