This work presents a fractional-N digital phase-locked loop (DPLL) characterized by low jitter and small area, featuring fast multi-variable calibration. To minimize the use of silicon area, the LC voltage-controlled oscillator (VCO) incorporated a compact three-turn inductor. Then, to still achieve low jitter, the bandwidth of the PLL was designed to be wide to suppress the poor phase noise of this VCO. To mitigate in-band noise, a digital-to-time converter (DTC) was employed to cancel the quantization noise (Q-noise) from the $\Delta \Sigma$ M, and a phase selector (PSEL) was used to reduce the thermal noise of the DTC. The effectiveness of these jitter-reduction techniques relies on digital background calibration. However, conventional multi-variable calibrators (MVCs), which utilize the least-mean-squares (LMS) algorithm, suffer from a prolonged convergence time. To overcome this limitation, this work introduced a recursive least-squares (RLS)-based MVC using a dichotomous coordinate descent (DCD) algorithm that can facilitate rapid calibration at a moderate implementation cost. The proposed DCD-RLS MVC achieved a calibration time of less than $7.2~{\mu }$ s, which was 40 times faster than the LMS MVC. The DPLL of this work achieved 88 fsrms jitter at a near-integer-N channel with 68-dBc fractional spurs. Fabricated using a 40-nm CMOS process, it occupied only a 0.12-mm2 active area and consumed 15.7 mW of power.