This article covers a synthesizing methodology for addressing harmonic rejection (HR) in hard-switching passive mixers. The integration of bottom and top plate mixing provides HR at both the antenna node and the output of the mixer in a passive and low-loss manner. A prototype mixer-first receiver (RX) in 45-nm partially depleted silicon-on-insulator (PD-SOI) is implemented, consuming 34.8–64.5 mW for clock frequencies ( $f_{\text {LO}}$ ) of 0.25–4 GHz and occupying an active area of 0.68 mm2. Due to the passive and early HR, it achieves an exceptional in-band (IB) harmonic blocker 1-dB compression point (B1 dB) of +14/+16.5 dBm at the third/fifth harmonics at a clock frequency of 1 GHz. Notably, with blocker powers up to 5 and 6.5 dBm at $3f_{\text {LO}}$ and $5f_{\text {LO}}$ , respectively, the harmonic blocker noise figure (BNF) only deteriorates by 3 dB at a clock frequency of 1 GHz. The minimal overhead of components facilitates the seamless incorporation of HR in widely tunable RXs and benefits from scaling.