This paper presents a modified two-stage comb decimation structure for Sigma-Delta Analog-to-Digital Converters (ADC) with high decimation factor, which can be implemented as a power of two. The proposed structure exhibits a decreased passband droop, as well as increased attenuations in the folding bands compared with the power and area efficient structures recently proposed in the literature. This is achieved by introducing a simple corrector filter at second CIC (Cascaded-Integrator-Comb) stage, such that it works at the rate, which is less than the high input rate by half of the decimation factor. The corrector filters depend only on the number of the cascaded equivalent combs. In that way the same corrector can be used for the comb decimator with different decimation factors but with the equal number of the cascaded combs. The comparison with the power and area efficient comb-based structures from literature, and the VHDL implementation, confirm the efficiency of the proposed structure.