Abstract:
This paper presents a simple circuital technique to design efficient pulse triggered flip-flops. The proposed approach aims at considerably alleviating the detrimental ef...Show MoreMetadata
Abstract:
This paper presents a simple circuital technique to design efficient pulse triggered flip-flops. The proposed approach aims at considerably alleviating the detrimental effects of current contention mechanisms, occurring at critical switching nodes during an output switching. In this way, both latency and power consumption are reduced. The proposed approach is assessed by means of simulations in 90-nm ST commercial CMOS technology. When applied to some recently proposed implicit pulse triggered flip-flop architectures, the suggested design strategy, allows speed to be improved up to 13% and power-delay-product to be lowered down to 14%. Moreover, also the process variation tolerance is considerably improved.
Date of Conference: 25-28 February 2014
Date Added to IEEE Xplore: 26 May 2014
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