Technology evolution brings new challenges to integrated circuits (IC) design. Parameter variation and complex design rules demand a great effort to create suitable design approaches to ensure manufacturability. Regular layout techniques allow a more accurate estimate of the circuit power and delay in early design steps. In this context, this work presents an evaluation of a set of basic cells candidates to integrate a 32nm high performance cell library in a regular layout synthesis flow. Considering a delay optimization flow, Inverters, NAND2 and NOR2 gates in CMOS bulk technology have shown better dynamic and static power results, when compared with predictive FinFET technologies.