The design and implementation of a dedicated hardware on an FPGA for the acquisition stage of Global Navigation Satellite Systems (GNSS) receivers are presented in this paper. The acquisition is an unavoidable processing stage for any GNSS receiver because it allows to detect the satellites and to do a first synchronization with the received signals. The current GNSS use spread spectrum and they have one or more code signals which are used to expand the spectrum. The phase or delay in which these signals arrive and the frequency deviation produced by the Doppler effect are the two main parameters that the receiver needs to find for synchronizing with the signal of a given satellite. Depending on the GNSS and on the reception conditions, the acquisition stage may require an excessive processing time for some applications. The design presented in this paper uses a Fast Fourier Transform (FFT) core which reduces significantly the processing time of the acquisition stage compared with the traditional methods. Also, it includes an interface with the AMBA bus which allows to control it from an embedded compatible microprocessor.