Future dark silicon chip-multiprocessors (CMPs) consist of many cores and uncores where only a few of them can be simultaneously powered on or utilized within the peak power. In this paper, we present a run-time convex optimization to reconfigure hybrid cache hierarchy and 3D NoC based CMP to minimize the power consumption and improves chip performance. The proposed approach dynamically estimate the read and write frequency of memory banks for next time interval and reconfigure the 3D chip by darkening or activating the DRAM/STT-RAM banks and TSV. Experimental result on PARSEC benchmark shows that the runtime reconfigurable approach improves the power consumption by about 39% on average.