Test sequences for interconnection testing in network-on-chips (NoC) are usually small. However, to ensure a good fault coverage, the sequence is usually re-applied for a number of paths configurations in the network. In this paper we first analyze the test configuration time required for a functional test strategy devised for mesh NoCs and we show that this time, specially for BIST-based solutions, may become the main bottleneck for overall test time reduction. We then analyze, in terms of area overhead and resulting test time, three alternatives for the implementation of the configuration logic for the test infrastructure. We conclude that boundary scan can be a very interesting solution for test configuration also in NoC testing, leading to a reduced test time and a programmable and reusable strategy.