Due to high sensitivity to process, supply, and temperature variations, deep scaled technologies are losing appeal. Analog and mixed-signal circuits have failed to exploit high speed and low noise properties of these technologies due to marginalities, whereas variations in leakage current and delay have made digital design extremely challenging. Consequently, there is an increasing need for a new design methodology that can provide high yield and improved reliability under PVT variations. Among several post-fabrication calibration strategies, self-healing, which is based on real-time sensing and built-in feedback, has generated great interest because of the ability to dynamically adapt to parametric variations. This paper examines current built-in variation-aware and ad-hoc self-healing designs, and discusses the challenges and strategies in developing a coherent self-healing methodology for system-on-chip (SoC) design in deep-scaled CMOS technologies.